Tessellated Intelligence System Best Practices - Patterns of Node Communication

This is an (eventually) comprehensive spoiler for Zachtronics’ game TIS-100, with notes on the system architecture, some common optimization techniques, and annotated solutions for each program.

Part I: General Information

Chapter 1: Implementation Details

This chapter documents various syntax quirks and undefined behaviors, such as integer overflows (everything is clipped to +/- 999), segfaults (can’t happen), and multiple simultaneous reads and writes to a Stack Memory Node.

Chapter 2: Instruction Timings

In short: Writing to a port takes two cycles (or more if it blocks) unless a Stack Memory Node is doing the writing. Reading from a port takes one cycle (or more if it blocks). Everything else takes one cycle.

Part II: TIS-100 Spoilers

Chapter 3: Getting Started

Covers segments 00150 (Self-Test Diagnostic) through 22280 (Signal Multiplexer).

An introduction to loops, parallelization using ANY, and switch statements with JRO.

Chapter 4: Learning about Pipelining

Covers segments 30647 (Sequence Generator) through 33762 (Interrupt Handler).

It’s like parallelism, but in series!

Chapter 5: Using Stack Memory Nodes

Covers segments 40196 (Signal Pattern Detector) through 43786 (Signal Multiplier).

State machines; avoiding gratuitous SWP/SAVs; preventing stack underflows without using a counter.

Chapter 6: Pretty Pictures

Covers segments 50370 (Image Test Pattern 1) through 53897 (Histogram Viewer).

Chapter 7: Algorithms

Covers segments 60099 (Signal Window Filter) through 63534 (Sequence Sorter).

Here’s where things really start to get complicated.

Chapter 8: The End

Covers segments 70601 [3 WORDS REDACTED] and UNKNOWN [2 WORDS REDACTED].

What really happened to Uncle Randy? And who built this machine anyway?

Part III: TIS-NET Spoilers

Coming soon!



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